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| Features * Single 2.3V - 3.6V or 2.7V - 3.6V Supply * Serial Peripheral Interface (SPI) Compatible - Supports SPI Modes 0 and 3 * 66 MHz Maximum Operating Frequency * - Clock-to-Output (tV) of 6 ns Maximum Flexible, Optimized Erase Architecture for Code + Data Storage Applications - Uniform 4-Kbyte Block Erase - Uniform 32-Kbyte Block Erase - Uniform 64-Kbyte Block Erase - Full Chip Erase Individual Sector Protection with Global Protect/Unprotect Feature - Four Sectors of 64 Kbytes Each Hardware Controlled Locking of Protected Sectors via WP Pin 128-Byte Programmable OTP Security Register Flexible Programming - Byte/Page Program (1 to 256 Bytes) Fast Program and Erase Times - 1.0 ms Typical Page Program (256 Bytes) Time - 50 ms Typical 4-Kbyte Block Erase Time - 250 ms Typical 32-Kbyte Block Erase Time - 450 ms Typical 64-Kbyte Block Erase Time Automatic Checking and Reporting of Erase/Program Failures JEDEC Standard Manufacturer and Device ID Read Methodology Low Power Dissipation - 7 mA Active Read Current (Typical at 20 MHz) - 15 A Deep Power-Down Current (Typical) Endurance: 100,000 Program/Erase Cycles Data Retention: 20 Years Complies with Full Industrial Temperature Range Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options - 8-lead SOIC (150-mil Wide) - 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm) * * * * * 2-Megabit 2.3-volt or 2.7-volt Minimum SPI Serial Flash Memory AT25DF021 * * * * * * * 1. Description The AT25DF021 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF021, with its erase granularity as small as 4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. 3677D-DFLASH-04/09 The physical sectoring and the erase block sizes of the AT25DF021 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. The AT25DF021 also offers a sophisticated method for protecting individual sectors against erroneous or malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. This is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. In addition to individual sector protection capabilities, the AT25DF021 incorporates Global Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors do not have to be unprotected one-by-one prior to initial programming. The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. Specifically designed for use in 2.5-volt or 3-volt systems, the AT25DF021 supports read, program, and erase operations with a supply voltage range of 2.3V to 3.6V or 2.7V to 3.6V. No separate voltage is required for programming and erasing. 2 AT25DF021 3677D-DFLASH-04/09 AT25DF021 2. Pin Descriptions and Pinouts Table 2-1. Symbol Pin Descriptions Name and Function CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched in on the rising edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted). SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state whenever the device is deselected (CS is deasserted). WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to "Protection Commands and Features" on page 12 for more details on protection features and the WP pin. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state. Asserted State Type CS Low Input SCK - Input SI - Input SO - Output WP Low Input HOLD The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. A Hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. Please refer to "Hold" on page 29 for additional details on the Hold operation. The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However, it is recommended that the HOLD pin also be externally connected to VCC whenever possible. Low Input VCC DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. GROUND: The ground reference for the power supply. GND should be connected to the system ground. - Power GND - Power 3 3677D-DFLASH-04/09 Figure 2-1. 8-SOIC Top View CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI Figure 2-2. 8-UDFN (Top View) CS SO WP GND 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 3. Block Diagram Figure 3-1. Block Diagram CS CONTROL AND PROTECTION LOGIC I/O BUFFERS AND LATCHES SCK SI SO INTERFACE CONTROL AND LOGIC SRAM DATA BUFFER Y-DECODER Y-GATING ADDRESS LATCH WP HOLD X-DECODER FLASH MEMORY ARRAY 4. Memory Array To provide the greatest flexibility, the memory array of the AT25DF021 can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations. The size of the physical sectors is optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. The Memory Architecture Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector. 4 AT25DF021 3677D-DFLASH-04/09 AT25DF021 Figure 4-1. Memory Architecture Diagram Block Erase Detail Internal Sectoring for Sector Protection Function 64KB 32KB Block Erase Block Erase (D8h Command) (52h Command) 4KB Block Erase (20h Command) 4KB 4KB 4KB 32KB 4KB 4KB 4KB 4KB 64KB (Sector 3) 64KB 4KB 4KB 4KB 4KB 32KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 32KB 4KB 4KB 4KB 4KB 64KB (Sector 2) 64KB 4KB 4KB 4KB 4KB 32KB 4KB 4KB 4KB 4KB 4KB Block Address Range 03FFFFh - 03F000h 03EFFFh - 03E000h 03DFFFh - 03D000h 03CFFFh - 03C000h 03BFFFh - 03B000h 03AFFFh - 03A000h 039FFFh - 039000h 038FFFh - 038000h 037FFFh - 037000h 036FFFh - 036000h 035FFFh - 035000h 034FFFh - 034000h 033FFFh - 033000h 032FFFh - 032000h 031FFFh - 031000h 030FFFh - 030000h 02FFFFh - 02F000h 02EFFFh - 02E000h 02DFFFh - 02D000h 02CFFFh - 02C000h 02BFFFh - 02B000h 02AFFFh - 02A000h 029FFFh - 029000h 028FFFh - 028000h 027FFFh - 027000h 026FFFh - 026000h 025FFFh - 025000h 024FFFh - 024000h 023FFFh - 023000h 022FFFh - 022000h 021FFFh - 021000h 020FFFh - 020000h 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 4KB 4KB 4KB 32KB 4KB 4KB 4KB 4KB 64KB (Sector 0) 64KB 4KB 4KB 4KB 4KB 32KB 4KB 4KB 4KB 4KB 4KB 00FFFFh - 00F000h 00EFFFh - 00E000h 00DFFFh - 00D000h 00CFFFh - 00C000h 00BFFFh - 00B000h 00AFFFh - 00A000h 009FFFh - 009000h 008FFFh - 008000h 007FFFh - 007000h 006FFFh - 006000h 005FFFh - 005000h 004FFFh - 004000h 003FFFh - 003000h 002FFFh - 002000h 001FFFh - 001000h 000FFFh - 000000h 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 0017FFh - 001700h 0016FFh - 001600h 0015FFh - 001500h 0014FFh - 001400h 0013FFh - 001300h 0012FFh - 001200h 0011FFh - 001100h 0010FFh - 001000h 000FFFh - 000F00h 000EFFh - 000E00h 000DFFh - 000D00h 000CFFh - 000C00h 000BFFh - 000B00h 000AFFh - 000A00h 0009FFh - 000900h 0008FFh - 000800h 0007FFh - 000700h 0006FFh - 000600h 0005FFh - 000500h 0004FFh - 000400h 0003FFh - 000300h 0002FFh - 000200h 0001FFh - 000100h 0000FFh - 000000h Page Program Detail 1-256 Byte Page Program (02h Command) 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes Page Address Range 03FFFFh - 03FF00h 03FEFFh - 03FE00h 03FDFFh - 03FD00h 03FCFFh - 03FC00h 03FBFFh - 03FB00h 03FAFFh - 03FA00h 03F9FFh - 03F900h 03F8FFh - 03F800h 03F7FFh - 03F700h 03F6FFh - 03F600h 03F5FFh - 03F500h 03F4FFh - 03F400h 03F3FFh - 03F300h 03F2FFh - 03F200h 03F1FFh - 03F100h 03F0FFh - 03F000h 03EFFFh - 03EF00h 03EEFFh - 03EE00h 03EDFFh - 03ED00h 03ECFFh - 03EC00h 03EBFFh - 03EB00h 03EAFFh - 03EA00h 03E9FFh - 03E900h 03E8FFh - 03E800h *** *** *** *** *** 5 3677D-DFLASH-04/09 5. Device Operation The AT25DF021 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25DF021 via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF021 supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. Figure 5-1. CS SPI Mode 0 and 3 SCK SI MSB LSB SO MSB LSB 6. Commands and Addressing A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25DF021 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation. Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0. Since the upper address limit of the AT25DF021 memory array is 03FFFFh, address bits A23-A18 are always ignored by the device. 6 AT25DF021 3677D-DFLASH-04/09 AT25DF021 Table 6-1. Command Read Commands Read Array Program and Erase Commands Block Erase (4 Kbytes) Block Erase (32 Kbytes) Block Erase (64 Kbytes) Chip Erase Byte/Page Program (1 to 256 Bytes) Protection Commands Write Enable Write Disable Protect Sector Unprotect Sector Global Protect/Unprotect Read Sector Protection Registers Security Commands Program OTP Security Register Read OTP Security Register Status Register Commands Read Status Register Write Status Register Miscellaneous Commands Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down 9Fh B9h ABh 1001 1111 1011 1001 1010 1011 Up to 66 MHz Up to 66 MHz Up to 66 MHz 0 0 0 0 0 0 1 to 4 0 0 05h 01h 0000 0101 0000 0001 Up to 66 MHz Up to 66 MHz 0 0 0 0 1+ 1 9Bh 77h 1001 1011 0111 0111 Up to 66 MHz Up to 66 MHz 3 3 0 2 1+ 1+ 3Ch 0011 1100 06h 04h 36h 39h 0000 0110 0000 0100 0011 0110 0011 1001 Up to 66 MHz Up to 66 MHz Up to 66 MHz Up to 66 MHz 0 0 3 3 0 0 0 0 0 0 0 0 20h 52h D8h 60h C7h 02h 0010 0000 0101 0010 1101 1000 0110 0000 1100 0111 0000 0010 Up to 66 MHz Up to 66 MHz Up to 66 MHz Up to 66 MHz Up to 66 MHz Up to 66 MHz 3 3 3 0 0 3 0 0 0 0 0 0 0 0 0 0 0 1+ 0Bh 03h 0000 1011 0000 0011 Up to 66 MHz Up to 33 MHz 3 3 1 0 1+ 1+ Command Listing Opcode Clock Frequency Address Bytes Dummy Bytes Data Bytes Use Write Status Register Command Up to 66 MHz 3 0 1+ 7 3677D-DFLASH-04/09 7. Read Commands 7.1 Read Array The Read Array command can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. The device incorporates an internal address counter that automatically increments on every clock cycle. Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each opcode depends on the maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock frequency up to the maximum specified by fCLK, and the 03h opcode can be used for lower frequency read operations up to the maximum specified by fRDLF. To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. Following the three address bytes, an additional dummy byte needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation. After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in, additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte (03FFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array. Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-1. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Read Array - 0Bh Opcode SCK OPCODE ADDRESS BITS A23-A0 0 1 1 A MSB DON'T CARE A A X MSB SI 0 MSB 0 0 0 1 A A A A A A X X X X X X X DATA BYTE 1 SO HIGH-IMPEDANCE D MSB D D D D D D D D MSB D Figure 7-2. Read Array - 03h Opcode CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE ADDRESS BITS A23-A0 0 1 1 A MSB SI 0 MSB 0 0 0 0 A A A A A A A A DATA BYTE 1 SO HIGH-IMPEDANCE D MSB D D D D D D D D MSB D 8 AT25DF021 3677D-DFLASH-04/09 AT25DF021 8. Program and Erase Commands 8.1 Byte/Page Program The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into previously erased memory locations. An erased memory location is one that has all eight bits set to the logical "1" state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write Enable command must have been previously issued to the device (see "Write Enable" on page 12) to set the Write Enable Latch (WEL) bit of the Status Register to a logical "1" state. To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer. If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer. When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate memory array locations based on the starting address specified by A23-A0 and the number of data bytes sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in a time of tPP or tBP if only programming a single byte. The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. In addition, if the address specified by A23-A0 points to a memory location within a sector that is in the protected state (see "Protect Sector" on page 13), then the Byte/Page Program command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical "0" state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or because the memory location to be programmed is protected. While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to determine if the data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status Register will be reset back to the logical "0" state. The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register. 9 3677D-DFLASH-04/09 Figure 8-1. Byte Program CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 SCK OPCODE ADDRESS BITS A23-A0 0 1 0 A MSB DATA IN A A D MSB SI 0 MSB 0 0 0 0 A A A A A A D D D D D D D SO HIGH-IMPEDANCE Figure 8-2. Page Program CS 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39 SCK OPCODE ADDRESS BITS A23-A0 0 1 0 A MSB DATA IN BYTE 1 D MSB DATA IN BYTE n D D MSB SI 0 MSB 0 0 0 0 A A A A A D D D D D D D D D D D D D SO HIGH-IMPEDANCE 8.2 Block Erase A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical "1" state) in a single operation by using one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical "1" state. To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the 4-, 32-, or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally selftimed and should take place in a time of tBLKE. Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values can be either a logical "1" or "0". For a 32-Kbyte erase, address bits A14-A0 will be ignored, and for a 64-Kbyte erase, address bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. 10 AT25DF021 3677D-DFLASH-04/09 AT25DF021 If the address specified by A23-A0 points to a memory location within a sector that is in the protected state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical "0" state if the erase cycle aborts due to an incomplete address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is protected. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical "0" state. The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-3. Block Erase CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE ADDRESS BITS A23-A0 C C A MSB SI C MSB C C C C C A A A A A A A A A A A SO HIGH-IMPEDANCE 8.3 Chip Erase The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical "1" state. Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase the entire memory array. The erasing of the device is internally self-timed and should take place in a time of tCHPE. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if any sector of the memory array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical "0" state if the CS pin is deasserted on uneven byte boundaries or if a sector is in the protected state. 11 3677D-DFLASH-04/09 While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tCHPE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical "0" state. The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-4. Chip Erase CS 0 1 2 3 4 5 6 7 SCK OPCODE SI C MSB C C C C C C C SO HIGH-IMPEDANCE 9. Protection Commands and Features 9.1 Write Enable The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical "1" state. The WEL bit must be set before a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Program OTP Security Register, or Write Status Register command can be executed. This makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to the issuance of one of these commands, then the command will not be executed. To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical "1". The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. Write Enable CS 0 1 2 3 4 5 6 7 SCK OPCODE SI 0 MSB 0 0 0 0 1 1 0 SO HIGH-IMPEDANCE 12 AT25DF021 3677D-DFLASH-04/09 AT25DF021 9.2 Write Disable The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical "0" state. With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, Program OTP Security Register, and Write Status Register commands will not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to the WEL bit section of the Status Register description. To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical "0". The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-2. Write Disable CS 0 1 2 3 4 5 6 7 SCK OPCODE SI 0 MSB 0 0 0 0 1 0 0 SO HIGH-IMPEDANCE 9.3 Protect Sector Every physical 64-Kbyte sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector. Upon device power-up, each Sector Protection Register will default to the logical "1" state indicating that all sectors are protected and cannot be programmed or erased. Issuing the Protect Sector command to a particular sector address will set the corresponding Sector Protection Register to the logical "1" state. The following table outlines the two states of the Sector Protection Registers. Table 9-1. Value 0 1 Sector Protection Register Values Sector Protection Status Sector is unprotected and can be programmed and erased. Sector is protected and cannot be programmed or erased. This is the default state. Before the Protect Sector command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical "1". To issue the Protect Sector command, the CS pin must first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes designating any address within the sector to be protected. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the physical sector addressed by A23-A0 will be set to the logical "1" state, and the sector itself will then be protected from 13 3677D-DFLASH-04/09 program and erase operations. In addition, the WEL bit in the Status Register will be reset back to the logical "0" state. The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation. When the device aborts the Protect Sector operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical "0". As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector Protection Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the Status Register (please refer to the Status Register description for more details). If the Sector Protection Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical "0" and return to the idle state once the CS pin has been deasserted. Figure 9-3. Protect Sector CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE ADDRESS BITS A23-A0 1 1 0 A MSB SI 0 MSB 0 1 1 0 A A A A A A A A A A A SO HIGH-IMPEDANCE 9.4 Unprotect Sector Issuing the Unprotect Sector command to a particular sector address will reset the corresponding Sector Protection Register to the logical "0" state (see Table 9-1 for Sector Protection Register values). Every physical sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software protection of a sector. Before the Unprotect Sector command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical "1". To issue the Unprotect Sector command, the CS pin must first be asserted and the opcode of 39h must be clocked into the device. After the opcode has been clocked in, the three address bytes designating any address within the sector to be unprotected must be clocked in. Any additional data clocked into the device after the address bytes will be ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the sector addressed by A23-A0 will be reset to the logical "0" state, and the sector itself will be unprotected. In addition, the WEL bit in the Status Register will be reset back to the logical "0" state. The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical "0". As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Protection Registers can themselves be locked from updates by using the SPRL (Sector Protection 14 AT25DF021 3677D-DFLASH-04/09 AT25DF021 Registers Locked) bit of the Status Register (please refer to the Status Register description for more details). If the Sector Protection Registers are locked, then any attempts to issue the Unprotect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical "0" and return to the idle state once the CS pin has been deasserted. Figure 9-4. Unprotect Sector CS 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 SCK OPCODE ADDRESS BITS A23-A0 0 0 1 A MSB SI 0 MSB 0 1 1 1 A A A A A A A A A A A SO HIGH-IMPEDANCE 9.5 Global Protect/Unprotect The Global Protect and Global Unprotect features can work in conjunction with the Protect Sector and Unprotect Sector functions. For example, a system can globally protect the entire memory array and then use the Unprotect Sector command to individually unprotect certain sectors and individually reprotect them later by using the Protect Sector command. Likewise, a system can globally unprotect the entire memory array and then individually protect certain sectors as needed. Performing a Global Protect or Global Unprotect is accomplished by writing a certain combination of data to the Status Register using the Write Status Register Byte 1 command (see "Write Status Register" on page 25 for command execution details). The Write Status Register command is also used to modify the SPRL (Sector Protection Registers Locked) bit to control hardware and software locking. To perform a Global Protect, the appropriate WP pin and SPRL conditions must be met, and the system must write a logical "1" to bits 5, 4, 3, and 2 of the first byte of the Status Register. Conversely, to perform a Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical "0" to bits 5, 4, 3, and 2 of the first byte of the Status Register. Table 9-2 details the conditions necessary for a Global Protect or Global Unprotect to be performed. 15 3677D-DFLASH-04/09 Table 9-2. Valid SPRL and Global Protect/Unprotect Conditions New Write Status Register Byte 1 Data Bit 76543210 0x0000xx 0x0001xx 0x1110xx 0x1111xx Protection Operation Global Unprotect - all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect - all Sector Protection Registers set to 1 Global Unprotect - all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect - all Sector Protection Registers set to 1 WP State Current SPRL Value New SPRL Value 0 0 0 0 0 1 1 1 1 1 0 0 1x0000xx 1x0001xx 1x1110xx 1x1111xx No change to the current protection level. All sectors currently protected will remain protected and all sectors currently unprotected will remain unprotected. 0 1 xxxxxxxx The Sector Protection Registers are hard-locked and cannot be changed when the WP pin is LOW and the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur. In addition, the SPRL bit cannot be changed (the WP pin must be HIGH in order to change SPRL back to a 0). Global Unprotect - all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect - all Sector Protection Registers set to 1 Global Unprotect - all Sector Protection Registers reset to 0 No change to current protection. No change to current protection. No change to current protection. Global Protect - all Sector Protection Registers set to 1 No change to the current protection level. All sectors currently protected will remain protected, and all sectors currently unprotected will remain unprotected. The Sector Protection Registers are soft-locked and cannot be changed when the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur. However, the SPRL bit can be changed back to a 0 from a 1 since the WP pin is HIGH. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from a 1 to a 0. 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0x0000xx 0x0001xx 0x1110xx 0x1111xx 1 0 1x0000xx 1x0001xx 1x1110xx 1x1111xx 0x0000xx 0x0001xx 0x1110xx 0x1111xx 1 1 1x0000xx 1x0001xx 1x1110xx 1x1111xx Essentially, if the SPRL bit of the Status Register is in the logical "0" state (Sector Protection Registers are not locked), then writing a 00h to the first byte of the Status Register will perform a Global Unprotect without changing the state of the SPRL bit. Similarly, writing a 7Fh to the first byte of the Status Register will perform a Global Protect and keep the SPRL bit in the logical "0" state. The SPRL bit can, of course, be changed to a logical "1" by writing an FFh if software-locking or hardware-locking is desired along with the Global Protect. If the desire is to only change the SPRL bit without performing a Global Protect or Global Unprotect, then the system can simply write a 0Fh to the first byte of the Status Register to change the 16 AT25DF021 3677D-DFLASH-04/09 AT25DF021 SPRL bit from a logical "1" to a logical "0" provided the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from a logical "0" to a logical "1" without affecting the current sector protection status (no changes will be made to the Sector Protection Registers). When writing to the first byte of the Status Register, bits 5, 4, 3, and 2 will not actually be modified but will be decoded by the device for the purposes of the Global Protect and Global Unprotect functions. Only bit 7, the SPRL bit, will actually be modified. Therefore, when reading the first byte of the Status Register, bits 5, 4, 3, and 2 will not reflect the values written to them but will instead indicate the status of the WP pin and the sector protection status. Please refer to "Read Status Register" on page 22 and Table 11-1 on page 22 for details on the Status Register format and what values can be read for bits 5, 4, 3, and 2. 9.6 Read Sector Protection Registers The Sector Protection Registers can be read to determine the current software protection status of each sector. Reading the Sector Protection Registers, however, will not determine the status of the WP pin. To read the Sector Protection Register for a particular sector, the CS pin must first be asserted and the opcode of 3Ch must be clocked in. Once the opcode has been clocked in, three address bytes designating any address within the sector must be clocked in. After the last address byte has been clocked in, the device will begin outputting data on the SO pin during every subsequent clock cycle. The data being output will be a repeating byte of either FFh or 00h to denote the value of the appropriate Sector Protection Register. Table 9-3. Output Data 00h FFh Read Sector Protection Register - Output Data Sector Protection Register Value Sector Protection Register value is 0 (sector is unprotected). Sector Protection Register value is 1 (sector is protected). Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bits in the Status Register can be read to determine if all, some, or none of the sectors are software protected (refer to "Read Status Register" on page 22 for more details). Figure 9-5. Read Sector Protection Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 SCK OPCODE ADDRESS BITS A23-A0 1 0 0 A MSB SI 0 MSB 0 1 1 1 A A A A A A A A DATA BYTE SO HIGH-IMPEDANCE D MSB D D D D D D D D MSB D 17 3677D-DFLASH-04/09 9.7 Protected States and the Write Protect (WP) Pin The WP pin is not linked to the memory array itself and has no direct effect on the protection status or lockdown status of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection Registers Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device. For hardware locking to be active, two conditions must be metthe WP pin must be asserted and the SPRL bit must be in the logical "1" state. When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit itself is also locked. Therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be locked in the unprotected state. These states cannot be changed as long as hardware locking is active, so the Protect Sector, Unprotect Sector, and Write Status Register commands will be ignored. In order to modify the protection status of a sector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must be reset back to the logical "0" state using the Write Status Register command. When resetting the SPRL bit back to a logical "0", it is not possible to perform a Global Protect or Global Unprotect at the same time since the Sector Protection Registers remain soft-locked until after the Write Status Register command has been executed. If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical "1", the only way to reset the bit back to the logical "0" state is to power-cycle the device. This allows a system to power-up with all sectors software protected but not hardware locked. Therefore, sectors can be unprotected and protected as needed and then hardware locked at a later time by simply setting the SPRL bit in the Status Register. When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the SPRL bit in the Status Register can still be set to a logical "1" to lock the Sector Protection Registers. This provides a software locking ability to prevent erroneous Protect Sector or Unprotect Sector commands from being processed. When changing the SPRL bit to a logical "1" from a logical "0", it is also possible to perform a Global Protect or Global Unprotect at the same time by writing the appropriate values into bits 5, 4, 3, and 2 of the first byte of the Status Register. Tables 9-4 and 9-5 detail the various protection and locking states of the device. Table 9-4. WP X (Don't Care) Note: 1. "n" represents a sector number Sector Protection Register States Sector Protection Register n(1) 0 1 Sector n(1) Unprotected Protected 18 AT25DF021 3677D-DFLASH-04/09 AT25DF021 Table 9-5. WP Hardware and Software Locking Locking SPRL Change Allowed Sector Protection Registers Unlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed. Locked in current state. Protect and Unprotect Sector commands will be ignored. Global Protect and Unprotect cannot be performed. Unlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed. Locked in current state. Protect and Unprotect Sector commands will be ignored. Global Protect and Unprotect cannot be performed. SPRL 0 0 Can be modified from 0 to 1 0 1 Hardware Locked Locked 1 0 Can be modified from 0 to 1 1 1 Software Locked Can be modified from 1 to 0 10. Security Commands 10.1 Program OTP Security Register The device contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. The OTP Security Register is independent of the main Flash memory array and is comprised of a total of 128 bytes of memory divided into two portions. The first 64 bytes (byte locations 0 through 63) of the OTP Security Register are allocated as a one-time user-programmable space. Once these 64 bytes have been programmed, they cannot be erased or reprogrammed. The remaining 64 bytes of the OTP Security Register (byte locations 64 through 127) are factory programmed by Atmel and will contain a unique value for each device. The factory programmed data is fixed and cannot be changed. Table 10-1. OTP Security Register Security Register Byte Number 0 1 ... 62 63 64 65 ... 126 127 One-Time User Programmable Factory Programmed by Atmel The user-programmable portion of the OTP Security Register does not need to be erased before it is programmed. In addition, the Program OTP Security Register command operates on the entire 64-byte user-programmable portion of the OTP Security Register at one time. Once the user-programmable space has been programmed with any number of bytes, the user-programmable space cannot be programmed again; therefore, it is not possible to only program the first two bytes of the register and then program the remaining 62 bytes at a later time. Before the Program OTP Security Register command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical "1". To program the OTP Security Register, the CS pin must first be asserted and an opcode of 9Bh must be clocked into the device followed by the three address bytes denoting the first byte 19 3677D-DFLASH-04/09 location of the OTP Security Register to begin programming at. Since the size of the user-programmable portion of the OTP Security Register is 64 bytes, the upper order address bits do not need to be decoded by the device. Therefore, address bits A23-A6 will be ignored by the device and their values can be either a logical "1" or "0". After the address bytes have been clocked in, data can then be clocked into the device and will be stored in the internal buffer. If the starting memory address denoted by A23-A0 does not start at the beginning of the OTP Security Register memory space (A5-A0 are not all 0), then special circumstances regarding which OTP Security Register locations to be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the 64-byte user-programmable space will wrap around back to the beginning of the OTP Security Register. For example, if the starting address denoted by A23-A0 is 00003Eh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at OTP Security Register addresses 00003Eh and 00003Fh while the last byte of data will be programmed at address 000000h. The remaining bytes in the OTP Security Register (addresses 000001h through 00003Dh) will not be programmed and will remain in the erased state (FFh). In addition, if more than 64 bytes of data are sent to the device, then only the last 64 bytes sent will be latched into the internal buffer. When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate OTP Security Register locations based on the starting address specified by A23-A0 and the number of data bytes sent to the device. If less than 64 bytes of data were sent to the device, then the remaining bytes within the OTP Security Register will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in a time of tOTPP. The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and the user-programmable portion of the OTP Security Register will not be programmed. The WEL bit in the Status Register will be reset back to the logical "0" state if the OTP Security Register program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or because the user-programmable portion of the OTP Security Register was previously programmed. While the device is programming the OTP Security Register, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tOTPP time to determine if the data bytes have finished programming. At some point before the OTP Security Register programming completes, the WEL bit in the Status Register will be reset back to the logical "0" state. If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte user programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed again. The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the contents of the buffer will be altered from its previous state when this command is issued. 20 AT25DF021 3677D-DFLASH-04/09 AT25DF021 Figure 10-1. Program OTP Security Register CS 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 39 SCK OPCODE ADDRESS BITS A23-A0 0 1 1 A MSB DATA IN BYTE 1 D MSB DATA IN BYTE n D D MSB SI 1 MSB 0 0 1 1 A A A A A D D D D D D D D D D D D D SO HIGH-IMPEDANCE 10.2 Read OTP Security Register The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum clock frequency specified by fCLK. To read the OTP Security Register, the CS pin must first be asserted and the opcode of 77h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the OTP Security Register. Following the three address bytes, two dummy bytes must be clocked into the device before data can be output. After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP Security Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security Register has been read, the device will continue reading back at the beginning of the register (000000h). No delays will be incurred when wrapping around from the end of the register to the beginning of the register. Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 10-2. Read OTP Security Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 SCK OPCODE ADDRESS BITS A23-A0 1 1 1 A MSB DON'T CARE A A X MSB SI 0 MSB 1 1 1 0 A A A A A A X X X X X X X X DATA BYTE 1 SO HIGH-IMPEDANCE D MSB D D D D D D D D MSB D 21 3677D-DFLASH-04/09 11. Status Register Commands 11.1 Read Status Register The Status Register can be read to determine the device's ready/busy status, as well as the status of many other functions such as Hardware Locking and Software Protection. The Status Register can be read at any time, including during an internally self-timed program or erase operation. To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the device. After the opcode has been clocked in, the device will begin outputting Status Register data on the SO pin during every subsequent clock cycle. After the last bit (bit 0) of the Status Register has been clocked out, the sequence will repeat itself starting again with bit 7 as long as the CS pin remains asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated, so each repeating sequence will output new data. Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 11-1. Bit(1) 7 6 5 SPRL RES EPE Status Register Format Name Sector Protection Registers Locked Reserved for future use Erase/Program Error Type(2) R/W R R 0 1 0 0 1 0 1 00 Description Sector Protection Registers are unlocked (default). Sector Protection Registers are locked. Reserved for future use. Erase or program operation was successful. Erase or program error detected. WP is asserted. WP is deasserted. All sectors are software unprotected (all Sector Protection Registers are 0). Some sectors are software protected. Read individual Sector Protection Registers to determine which sectors are protected. Reserved for future use. All sectors are software protected (all Sector Protection Registers are 1 - default). Device is not write enabled (default). Device is write enabled. Device is ready. Device is busy with an internal operation. 4 WPP Write Protect (WP) Pin Status R 3:2 SWP Software Protection Status R 01 10 11 1 WEL Write Enable Latch Status R 0 1 0 1 0 Notes: RDY/BSY Ready/Busy Status R 1. Only bit 7 of the Status Register will be modified when using the Write Status Register command. 2. R/W = Readable and writable R = Readable only 22 AT25DF021 3677D-DFLASH-04/09 AT25DF021 11.1.1 SPRL Bit The SPRL bit is used to control whether the Sector Protection Registers can be modified or not. When the SPRL bit is in the logical "1" state, all Sector Protection Registers are locked and cannot be modified with the Protect Sector and Unprotect Sector commands (the device will ignore these commands). In addition, the Global Protect and Global Unprotect features cannot be performed. Any sectors that are presently protected will remain protected, and any sectors that are presently unprotected will remain unprotected. When the SPRL bit is in the logical "0" state, all Sector Protection Registers are unlocked and can be modified (the Protect Sector and Unprotect Sector commands, as well as the Global Protect and Global Unprotect features, will be processed as normal). The SPRL bit defaults to the logical "0" state after device power-up. The Reset command has no effect on the SPRL bit. The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then the SPRL bit may only be changed from a logical "0" (Sector Protection Registers are unlocked) to a logical "1" (Sector Protection Registers are locked). In order to reset the SPRL bit back to a logical "0" using the Write Status Register command, the WP pin will have to first be deasserted. The SPRL bit is the only bit of the Status Register that can be user modified via the Write Status Register command. 11.1.2 EPE Bit The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the logical "1" state. The EPE bit will not be set if an erase or program operation aborts for any reason such as an attempt to erase or program a protected region, or if the WEL bit is not set prior to an erase or program operation. The EPE bit will be updated after every erase and program operation. 11.1.3 WPP Bit The WPP bit can be read to determine if the WP pin has been asserted or not. 11.1.4 SWP Bits The SWP bits provide feedback on the software protection status for the device. There are three possible combinations of the SWP bits that indicate whether none, some, or all of the sectors have been protected using the Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have been protected, then the individual Sector Protection Registers can be read with the Read Sector Protection Registers command to determine which sectors are in fact protected. 23 3677D-DFLASH-04/09 11.1.5 WEL Bit The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical "0" state, the device will not accept any Byte/Page Program, erase, Protect Sector, Unprotect Sector, Program OTP Security Register, or Write Status Register commands. The WEL bit defaults to the logical "0" state after a device power-up or reset operation. In addition, the WEL bit will be reset to the logical "0" state automatically under the following conditions: * Write Disable operation completes successfully * Write Status Register operation completes successfully or aborts * Protect Sector operation completes successfully or aborts * Unprotect Sector operation completes successfully or aborts * Program OTP Security Register operation completes successfully or aborts * Byte/Page Program operation completes successfully or aborts * Block Erase operation completes successfully or aborts * Chip Erase operation completes successfully or aborts * Hold condition aborts If the WEL bit is in the logical "1" state, it will not be reset to a logical "0" if an operation aborts due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Program OTP Security Register, or Write Status Register command must have been clocked into the device. 11.1.6 RDY/BSY Bit The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical "1" to a logical "0". Figure 11-1. Read Status Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SCK OPCODE SI 0 MSB 0 0 0 0 1 0 1 STATUS REGISTER DATA D MSB STATUS REGISTER DATA D D D MSB STATUS REGISTER DATA D D D MSB SO HIGH-IMPEDANCE D D D D D D D D D D D D D D D D D 24 AT25DF021 3677D-DFLASH-04/09 AT25DF021 11.2 Write Status Register The Write Status Register command is used to modify the SPRL bit of the Status Register and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Register command can be issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to a logical "1". To issue the Write Status Register command, the CS pin must first be asserted and the opcode of 01h must be clocked into the device followed by one byte of data. The one byte of data consists of the SPRL bit value, a don't care bit, four data bits to denote whether a Global Protect or Unprotect should be performed, and two additional don't care bits (see Table 11-2). Any additional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the SPRL bit in the Status Register will be modified, and the WEL bit in the Status Register will be reset back to a logical "0". The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before the Write Status Register command was executed (the prior state of the SPRL bit) will determine whether or not a Global Protect or Global Unprotect will be performed. Please refer to "Global Protect/Unprotect" on page 15 for more details. The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of the SPRL bit will not change, no potential Global Protect or Unprotect will be performed, and the WEL bit in the Status Register will be reset back to the logical "0" state. If the WP pin is asserted, then the SPRL bit can only be set to a logical "1". If an attempt is made to reset the SPRL bit to a logical "0" while the WP pin is asserted, then the Write Status Register Byte command will be ignored, and the WEL bit in the Status Register will be reset back to the logical "0" state. In order to reset the SPRL bit to a logical "0", the WP pin must be deasserted. Table 11-2. Bit 7 SPRL Write Status Register Format Bit 6 X Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 X Bit 0 X Global Protect/Unprotect Figure 11-2. Write Status Register CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK OPCODE STATUS REGISTER IN 0 1 D MSB SI 0 MSB 0 0 0 0 0 X D D D D X X SO HIGH-IMPEDANCE 25 3677D-DFLASH-04/09 12. Other Commands and Functions 12.1 Read Manufacturer and Device ID Identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. The identification method and the command opcode comply with the JEDEC standard for "Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices". The type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the vendor specific Extended Device Information. Since not all Flash devices are capable of operating at very high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably low clock frequency to ensure that all devices to be used in the application can be identified properly. Once the identification process is complete, the application can then increase the clock frequency to accommodate specific Flash devices that are capable of operating at the higher clock frequencies. To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into the device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two bytes of Device ID information. The fourth byte output will be the Extended Device Information String Length, which will be 00h indicating that no Extended Device Information follows. After the Extended Device Information String Length byte is output, the SO pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the SO pin and no data will be output. As indicated in the JEDEC standard, reading the Extended Device Information String Length and any subsequent data is optional. Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Table 12-1. 1 2 3 4 Manufacturer and Device ID Information Data Type Manufacturer ID Device ID (Part 1) Device ID (Part 2) Extended Device Information String Length Value 1Fh 43h 00h 00h Byte No. Table 12-2. Data Type Manufacturer ID Manufacturer and Device ID Details Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex Value 1Fh Details JEDEC Code: Family Code: Density Code: 0001 1111 (1Fh for Atmel) 010 (AT25DF/26DFxxx series) 00011 (2-Mbit) JEDEC Assigned Code 0 0 Family Code 0 1 Sub Code 0 0 0 0 0 0 0 0 1 1 1 Density Code 0 1 1 1 1 Device ID (Part 1) 43h Device ID (Part 2) Product Version Code 0 0 0 0 00h Sub Code: 000 (Standard series) Product Version: 00000 (Initial version) 26 AT25DF021 3677D-DFLASH-04/09 AT25DF021 Figure 12-1. Read Manufacturer and Device ID CS 0 6 7 8 14 15 16 22 23 24 30 31 32 38 SCK OPCODE SI 9Fh SO HIGH-IMPEDANCE 1Fh 43h 00h 00h MANUFACTURER ID DEVICE ID BYTE1 DEVICE ID BYTE2 EXTENDED DEVICE INFORMATION STRING LENGTH Note: Each transition shown for SI and SO represents one byte (8 bits) 12.2 Deep Power-Down During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to place the device into an even lower power consumption state called the Deep Power-Down mode. When the device is in the Deep Power-Down mode, all commands including the Read Status Register command will be ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode of B9h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the Deep Power-Down mode within the maximum time of tEDPD. The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode after a power-cycle. The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. 27 3677D-DFLASH-04/09 Figure 12-2. Deep Power-Down CS 0 1 2 3 4 5 6 7 tEDPD SCK OPCODE SI 1 MSB 0 1 1 1 0 0 1 SO HIGH-IMPEDANCE Active Current ICC Standby Mode Current Deep Power-Down Mode Current 12.3 Resume from Deep Power-Down In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down command must be issued. The Resume from Deep Power-Down command is the only command that the device will recognized while in the Deep Power-Down mode. To resume from the Deep Power-Down mode, the CS pin must first be asserted and opcode of ABh must be clocked into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is deasserted, the device will exit the Deep PowerDown mode within the maximum time of tRDPD and return to the standby mode. After the device has returned to the standby mode, normal command operations such as Read Array can be resumed. If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down mode. Figure 12-3. Resume from Deep Power-Down CS 0 1 2 3 4 5 6 7 tRDPD SCK OPCODE SI 1 MSB 0 1 0 1 0 1 1 SO HIGH-IMPEDANCE Active Current ICC Deep Power-Down Mode Current Standby Mode Current 28 AT25DF021 3677D-DFLASH-04/09 AT25DF021 12.4 Hold The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the erase cycle will continue until it is finished. The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode won't be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are asserted. While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode. To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won't end until the beginning of the next SCK low pulse. If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical "0" state. Figure 12-4. Hold Mode CS SCK HOLD Hold Hold Hold 29 3677D-DFLASH-04/09 13. System Considerations In an effort to continue our goal of maintaining world-class quality leadership, Atmel has been performing extensive testing on the AT25DF021 that would not normally be done with a Serial Flash device. The testing that has been performed on the AT25DF021 involved extensive, nonstop reading of the memory array on pre-conditioned devices. The pre-conditioning of the devices, which entailed erasing and programming the entire memory array 10,000 times, was done to simulate a customer environment and to exercise the memory cells to a certain degree. The non-stop reading of the devices was done in three levels of granularity, with the first level involving a continuous, looped read of 256 bytes (a single page) of memory, the second level involving a continuous, looped-read of a 4-Kbyte (16 pages) portion of memory, and the third level entailing non-stop reading of the entire memory array. Read operations were performed at both +25C and +125C and with a supply voltage of 3.7V, which exceeds the specified datasheet operating voltage range. The results of all of the extensive tests indicate that the contents of a portion of memory being read continuously could be altered after 800,000,000 read operations only if that portion of the memory was not erased or reprogrammed at all during the 800,000,000 read operations. If that portion of memory was reprogrammed at some point, then it would take another 800,000,000 read operations after reprogramming before the contents could potentially be altered. For example, if the Serial Flash is being used for boot code storage, then it would take 800,000,000 boot operations before that boot code may become altered, provided that the boot code was not updated or reprogrammed. If an application was to read the entire memory array non-stop at a clock frequency of 10MHz, it would take over 5 years to reach 800,000,000 read operations. Atmel firmly believes that this extended testing result should not be a cause for concern. We also believe that most, if not all, applications will never read the same portion of memory 800,000,000 times throughout the life of the application without ever updating that portion of memory. 30 AT25DF021 3677D-DFLASH-04/09 AT25DF021 14. Electrical Specifications 14.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground .....................................-0.6V to +4.1V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.5V 14.2 DC and AC Operating Range AT25DF021 (2.3V Version) AT25DF021 (2.7V Version) -40C to 85C 2.7V to 3.6V Operating Temperature (Case) VCC Power Supply Ind. -40C to 85C 2.3V to 3.6V 14.3 DC Characteristics Parameter Standby Current Deep Power-down Current Condition CS, WP, HOLD = VCC, all inputs at CMOS levels CS, WP, HOLD = VCC, all inputs at CMOS levels f = 66 MHz; IOUT = 0 mA; CS = VIL, VCC = Max f = 66 MHz; IOUT = 0 mA; CS = VIL, VCC = Max Min Typ 25 15 11 10 9 8 7 12 14 Max 50 25 16 15 14 12 10 18 20 1 1 0.3 x VCC mA mA A A V mA Units A A Symbol ISB IDPD ICC1 Active Current, Read Operation f = 50 MHz; IOUT = 0 mA; CS = VIL, VCC = Max f = 33 MHz; IOUT = 0 mA; CS = VIL, VCC = Max f = 20 MHz; IOUT = 0 mA; CS = VIL, VCC = Max ICC2 ICC3 ILI ILO VIL Active Current, Program Operation Active Current, Erase Operation Input Leakage Current Output Leakage Current Input Low Voltage CS = VCC, VCC = Max CS = VCC, VCC = Max VIN = CMOS levels VOUT = CMOS levels 31 3677D-DFLASH-04/09 14.3 VIH VOL VOH DC Characteristics (Continued) Parameter Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA; VCC = Min IOH = -100 A; VCC = Min VCC - 0.2V Condition Min 0.7 x VCC 0.4 Typ Max Units V V V Symbol 14.4 AC Characteristics - Maximum Clock Frequencies AT25DF021 (2.3V Version) AT25DF021 (2.7V Version) Min Max 66 33 Units MHz MHz Symbol fCLK fRDLF Parameter Maximum Clock Frequency for All Operations (excluding 03h opcode) Maximum Clock Frequency for 03h Opcode (Read Array - Low Frequency) Min Max 50 33 14.5 AC Characteristics - All Other Parameters AT25DF021 (2.3V Version) AT25DF021 (2.7V Version) Min 6.4 6.4 0.1 0.1 50 5 5 5 5 2 3 7 7 0 5 5 5 5 7 7 0 5 5 5 5 6 6 6 6 Max Units ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol tCLKH tCLKL tCLKR tCSH tCSLS tCSLH tCSHS tCSHH tDS tDH tDIS(1) tV(2) tOH tHLS tHLH tHHS tHHH tHLQZ(1) tHHQX (1) (1) Parameter Clock High Time Clock Low Time Clock Rise Time, Peak-to-Peak (Slew Rate) Clock Fall Time, Peak-to-Peak (Slew Rate) Chip Select High Time Chip Select Low Setup Time (relative to Clock) Chip Select Low Hold Time (relative to Clock) Chip Select High Setup Time (relative to Clock) Chip Select High Hold Time (relative to Clock) Data In Setup Time Data In Hold Time Output Disable Time Output Valid Time Output Hold Time HOLD Low Setup Time (relative to Clock) HOLD Low Hold Time (relative to Clock) HOLD High Setup Time (relative to Clock) HOLD High Hold Time (relative to Clock) HOLD Low to Output High-Z HOLD High to Output Low-Z Min 8.0 8.0 0.1 0.1 50 5 5 5 5 2 3 Max tCLKF(1) 32 AT25DF021 3677D-DFLASH-04/09 AT25DF021 14.5 AC Characteristics - All Other Parameters (Continued) AT25DF021 (2.3V Version) Symbol tWPS(1)(3) tWPH (1)(3) AT25DF021 (2.7V Version) Min 20 100 Max Units ns ns 20 20 3 30 ns ns s s Parameter Write Protect Setup Time Write Protect Hold Time Sector Protect Time (from Chip Select High) Sector Unprotect Time (from Chip Select High) Chip Select High to Deep Power-Down Chip Select High to Standby Mode Min 20 100 Max tSECP(1) tSECUP(1) tEDPD(1) tRDPD(1) Notes: 20 20 3 30 1. Not 100% tested (value guaranteed by design and characterization). 2. 15 pF load at frequencies above 66 MHz, 30 pF otherwise. 3. Only applicable as a constraint for the Write Status Register command when SPRL = 1. 14.6 tPP(1) tBP tBLKE(1) tCHPE Program and Erase Characteristics Parameter Page Program Time (256 Bytes) Byte Program Time 4 Kbytes Block Erase Time 32 Kbytes 64 Kbytes (1)(2) Symbol Min Typ 1.0 7 50 250 450 2.0 200 Max 5.0 Units ms s 200 600 950 3.5 500 200 sec s ns ms Chip Erase Time OTP Security Register Program Time Write Status Register Time tOTPP(1) tWRSR Note: (2) 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles. 2. Not 100% tested (value guaranteed by design and characterization). 14.7 tVCSL tPUW VPOR Power-up Conditions Parameter Minimum VCC to Chip Select Low Time Power-up Device Delay Before Program or Erase Allowed Power-on Reset Voltage 1.5 Min 1.2 10 2.2 Max Units ms ms V Symbol 33 3677D-DFLASH-04/09 14.8 Input Test Waveforms and Measurement Levels AC DRIVING LEVELS 0.9VCC VCC/2 0.1VCC AC MEASUREMENT LEVEL tR, tF < 2 ns (10% to 90%) 14.9 Output Test Load DEVICE UNDER TEST 15 pF (frequencies above 66 MHz) or 30pF 34 AT25DF021 3677D-DFLASH-04/09 AT25DF021 15. AC Waveforms Figure 15-1. Serial Input Timing tCSH CS tCSLS tCLKH tCSLH tCLKL tCSHH tCSHS SCK tDS tDH MSB LSB MSB SI SO HIGH-IMPEDANCE Figure 15-2. Serial Output Timing CS tCLKH tCLKL tDIS SCK SI tV tOH tV SO Figure 15-3. WP Timing for Write Status Register Command When SPRL = 1 CS t WPS t WPH WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE 0 0 X LSB OF WRITE STATUS REGISTER DATA BYTE MSB MSB OF NEXT OPCODE SO HIGH-IMPEDANCE 35 3677D-DFLASH-04/09 Figure 15-4. HOLD Timing - Serial Input CS SCK tHHH tHLS tHLH tHHS HOLD SI HIGH-IMPEDANCE SO Figure 15-5. HOLD Timing - Serial Output CS SCK tHHH tHLS tHLH tHHS HOLD SI tHLQZ tHHQX SO 36 AT25DF021 3677D-DFLASH-04/09 AT25DF021 16. Ordering Information 16.1 Ordering Code Detail AT 2 5DF 0 2 1 - SSHF - B Atmel Designator Shipping Carrier Option B = Bulk (tubes) Y = Bulk (trays) T = Tape and reel Product Family Operating Voltage Blank = 2.7V minimum (2.7V to 3.6V) F = 2.3V minimum (2.3V to 3.6V) Device Density 02 = 2-megabit Device Grade H = Green, NiPdAu lead finish, industrial temperature range (-40C to +85C) Interface 1 = Serial Package Option SS = 8-lead, 0.150" wide SOIC M = 8-pad 5 x 6 x 0.6 mm UDFN 16.2 Green Package Options (Pb/Halide-free/RoHS Compliant) Ordering Code Package 8S1 NiPdAu 8MA1 8S1 NiPdAu 8MA1 2.3V to 3.6V 50 2.7V to 3.6V 70 Industrial (-40C to +85C) Lead Finish Operating Voltage Max. Freq. (MHz) Operation Range AT25DF021-SSH-B AT25DF021-SSH-T AT25DF021-MH-Y AT25DF021-MH-T AT25DF021-SSHF-B AT25DF021-SSHF-T AT25DF021-MHF-Y AT25DF021-MHF-T Note: The shipping carrier option code is not marked on the devices. Package Type 8S1 8MA1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-pad, 5 x 6 x 0.6 mm, Thermally Enhanced Ultra Thin Dual Flat No Lead Package (UDFN) 37 3677D-DFLASH-04/09 17. Packaging Information 17.1 8S1 - JEDEC SOIC C 1 E E1 N L O TOP VIEW END VIEW e b A A1 SYMBOL A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM - MAX NOTE 0.10 0.25 D SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 3/17/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. C R 38 AT25DF021 3677D-DFLASH-04/09 AT25DF021 17.2 8MA1 - UDFN E C Pin 1 ID D SIDE VIEW y TOP VIEW A K 8 A1 E2 0.45 Pin #1 Notch (0.20 R) (Option B) Option A 1 Pin #1 Chamfer (C 0.35) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.45 0.00 0.35 NOM 0.55 0.02 0.40 0.152 REF 4.90 3.80 5.90 3.20 5.00 4.00 6.00 3.40 1.27 0.50 0.00 0.20 0.60 - - 0.75 0.08 - 5.10 4.20 6.10 3.60 MAX 0.60 0.05 0.48 NOTE 7 2 D2 6 3 e A A1 b C 5 4 D b L BOTTOM VIEW D2 E E2 e L y K 4/15/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) GPC YFG DRAWING NO. 8MA1 REV. D 39 3677D-DFLASH-04/09 18. Revision History Revision Level - Release Date A - February 2008 History Initial release Changed Deep Power-Down current specifications - Changed typical value from 4 A to 8 A - Changed maximum value from 8 A to 15 A Changed typical 64 KB Block Erase time from 400 ms to 450 ms Changed typical Chip Erase time from 1.5s to 2.0s Changed tVCSL time from 1.0 ms minimum to 1.2 ms minimum Changed VPOR maximum from 2.5V to 2.2V Removed "Preliminary" designation from datasheet Changed maximum clock frequency from 70 MHz to 66 MHz Changed maximum Standby Current value from 35 A to 50 A Changed Deep Power-Down Current specifications - Changed typical value from 8 A to 15 A - Changed maximum value from 15 A to 25 A Added System Considerations Section B - May 2008 C - September 2008 D - April 2009 40 AT25DF021 3677D-DFLASH-04/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support dataflash@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2009 Atmel Corporation. All rights reserved. Atmel(R), Atmel logo and combinations thereof, DataFlash (R) and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 3677D-DFLASH-04/09 |
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